Passing a hexadecimal value into a module

I created a module that accepts a wire [ 4 : 0 ] as input, and I'm using several instances of this module. But, I'm getting:

Syntax error in instance port expression(s)

whenever I pass a value that contains A-F. For example:

key_schedule i1(09); // works key_schedule i1(0A); // doesn't work key_schedule i1(15); // works key_schedule i1(1D); // doesn't work

If anyone knows what's wrong, I'd appreciate their help. 61.1k 19 19 gold badges 78 78 silver badges 122 122 bronze badges asked Jan 7, 2013 at 21:10 741 2 2 gold badges 7 7 silver badges 13 13 bronze badges

2 Answers 2

Verilog treats all bare numeric literals as decimal. A and D are not legal decimal values.

For hexadecimal literals, you need to specify the literal type using 'h :

key_schedule i1('h0A); // works key_schedule i1('h1D); // works

Refer to the IEEE Std (1800-2009, for example), section "Numbers".

The following code compiles for me without errors on 2 different simulators (Incisive and VCS):

module tb; key_schedule i1(5'h1A); key_schedule i2('h1A); endmodule module key_schedule (input [4:0] in); always @(in) $display(in); endmodule